comparator Project Status (05/16/2012 - 23:32:06)
Project File: VADER.xise Parser Errors: No Errors
Module Name: sha1 Implementation State: Placed and Routed
Target Device: xc3s50-5pq208
  • Errors:
 
Product Version:ISE 13.4
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 668 1,536 43%  
Number of 4 input LUTs 867 1,536 56%  
Number of occupied Slices 558 768 72%  
    Number of Slices containing only related logic 558 558 100%  
    Number of Slices containing unrelated logic 0 558 0%  
Total Number of 4 input LUTs 899 1,536 58%  
    Number used as logic 803      
    Number used as a route-thru 32      
    Number used as Shift registers 64      
Number of bonded IOBs 69 124 55%  
Number of BUFGMUXs 1 8 12%  
Average Fanout of Non-Clock Nets 3.25      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed 16. May 21:39:39 2012   
Translation ReportCurrentWed 16. May 21:39:45 2012   
Map ReportCurrentWed 16. May 21:39:54 2012   
Place and Route ReportCurrentWed 16. May 21:40:16 2012   
Power Report     
Post-PAR Static Timing ReportCurrentWed 16. May 21:40:18 2012   
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogCurrentWed 16. May 23:24:48 2012

Date Generated: 05/16/2012 - 23:32:43