VADERtest Project Status (05/17/2012 - 00:39:56)
Project File: VADER.xise Parser Errors: No Errors
Module Name: VADERtest Implementation State: Placed and Routed
Target Device: xc3s50-5pq208
  • Errors:
No Errors
Product Version:ISE 13.4
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 676 1,536 44%  
Number of 4 input LUTs 890 1,536 57%  
Number of occupied Slices 569 768 74%  
    Number of Slices containing only related logic 569 569 100%  
    Number of Slices containing unrelated logic 0 569 0%  
Total Number of 4 input LUTs 922 1,536 60%  
    Number used as logic 826      
    Number used as a route-thru 32      
    Number used as Shift registers 64      
Number of bonded IOBs 101 124 81%  
Number of BUFGMUXs 1 8 12%  
Average Fanout of Non-Clock Nets 3.21      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentThu 17. May 00:39:22 20120034 Infos (0 new)
Translation ReportCurrentThu 17. May 00:39:27 2012000
Map ReportCurrentThu 17. May 00:39:31 2012002 Infos (0 new)
Place and Route ReportCurrentThu 17. May 00:39:52 2012002 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentThu 17. May 00:39:55 2012006 Infos (0 new)
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateThu 17. May 01:02:57 2012

Date Generated: 05/17/2012 - 01:03:44