System Settings

 
Environment Settings
Environment Variable xst ngdbuild map par
LMC_HOME c:\altera\11.0\quartus\eda\sim_lib\excalibur\swift < data not available > < data not available > < data not available >
PATHEXT .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.PSC1
< data not available > < data not available > < data not available >
Path C:\Xilinx\13.4\ISE_DS\ISE\\lib\nt;
C:\Xilinx\13.4\ISE_DS\ISE\\bin\nt;
C:\Xilinx\13.4\ISE_DS\PlanAhead\bin;
C:\Xilinx\13.4\ISE_DS\ISE\bin\nt;
C:\Xilinx\13.4\ISE_DS\ISE\lib\nt;
C:\Xilinx\13.4\ISE_DS\common\bin\nt;
C:\Xilinx\13.4\ISE_DS\common\lib\nt;
C:\Program Files\FEKO\6.0\bin;
C:\WINDOWS\system32;
C:\WINDOWS;
C:\WINDOWS\system32\WBEM;
C:\bin;
C:\altera\quartus42\bin;
C:\altera\quartus42\eda\sim_lib\excalibur\swift\lib\pcnt.lib;
C:\WINDOWS\system32\WindowsPowerShell\v1.0;
C:\Program Files\IVI Foundation\IVI\bin;
C:\Program Files\IVI Foundation\VISA\WinNT\Bin\;
C:\PROGRA~1\IVIFOU~1\VISA\WinNT\Bin;
C:\Program Files\IVI Foundation\VISA\WinNT\Bin;
C:\Program Files\Microchip\MPLAB C32 Suite\bin;
C:\Program Files\Microchip\MPLAB IDE\VDI;
C:\Program Files\HI-TECH Software\PICC\PRO\9.65\bin
< data not available > < data not available > < data not available >
XILINX C:\Xilinx\13.4\ISE_DS\ISE\ < data not available > < data not available > < data not available >
XILINX_DSP C:\Xilinx\13.4\ISE_DS\ISE < data not available > < data not available > < data not available >
XILINX_PLANAHEAD C:\Xilinx\13.4\ISE_DS\PlanAhead < data not available > < data not available > < data not available >
 
Synthesis Property Settings
Switch Name Property Name Value Default Value
-ifn   sha1.prj  
-ifmt   mixed MIXED
-ofn   sha1  
-ofmt   NGC NGC
-p   xc3s50-5-pq208  
-top   sha1  
-opt_mode Optimization Goal Speed SPEED
-opt_level Optimization Effort 1 1
-iuc Use synthesis Constraints File NO NO
-keep_hierarchy Keep Hierarchy No NO
-netlist_hierarchy Netlist Hierarchy As_Optimized as_optimized
-rtlview Generate RTL Schematic Yes NO
-glob_opt Global Optimization Goal AllClockNets ALLCLOCKNETS
-read_cores Read Cores YES YES
-write_timing_constraints Write Timing Constraints NO NO
-cross_clock_analysis Cross Clock Analysis NO NO
-bus_delimiter Bus Delimiter <> <>
-slice_utilization_ratio Slice Utilization Ratio 100 100%
-bram_utilization_ratio BRAM Utilization Ratio 100 100%
-verilog2001 Verilog 2001 YES YES
-fsm_extract   YES YES
-fsm_encoding   Auto AUTO
-safe_implementation   No NO
-fsm_style   LUT LUT
-ram_extract   Yes YES
-ram_style   Auto AUTO
-rom_extract   Yes YES
-shreg_extract   YES YES
-rom_style   Auto AUTO
-auto_bram_packing   NO NO
-resource_sharing   YES YES
-async_to_sync   NO NO
-mult_style   Auto AUTO
-iobuf   YES YES
-max_fanout   500 500
-bufg   8 8
-register_duplication   YES YES
-register_balancing   No NO
-optimize_primitives   NO NO
-use_clock_enable   Yes YES
-use_sync_set   Yes YES
-use_sync_reset   Yes YES
-iob   Auto AUTO
-equivalent_register_removal   YES YES
-slice_utilization_ratio_maxmargin   5 0%
 
Operating System Information
Operating System Information xst ngdbuild map par
CPU Architecture/Speed Intel(R) Core(TM) i5 CPU 760 @ 2.80GHz/2792 MHz <  data not available  > <  data not available  > <  data not available  >
Host bluelabvbox <  data not available  > <  data not available  > <  data not available  >
OS Name Microsoft Windows XP Professional <  data not available  > <  data not available  > <  data not available  >
OS Release Service Pack 3 (build 2600) <  data not available  > <  data not available  > <  data not available  >