sha1 Project Status (05/16/2012 - 21:55:43)
Project File: VADER.xise Parser Errors: No Errors
Module Name: sha1 Implementation State: Placed and Routed
Target Device: xc7vx330t-3ffg1157
  • Errors:
 
Product Version:ISE 13.4
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 8 1,536 1%  
Number of 4 input LUTs 24 1,536 1%  
Number of occupied Slices 16 768 2%  
    Number of Slices containing only related logic 16 16 100%  
    Number of Slices containing unrelated logic 0 16 0%  
Total Number of 4 input LUTs 24 1,536 1%  
Number of bonded IOBs 99 124 79%  
Number of BUFGMUXs 1 8 12%  
Average Fanout of Non-Clock Nets 1.71      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed 16. May 23:31:51 2012   
Translation ReportCurrentWed 16. May 23:31:56 2012   
Map ReportCurrentWed 16. May 23:31:58 2012   
Place and Route ReportCurrentWed 16. May 23:32:04 2012   
Power Report     
Post-PAR Static Timing ReportCurrentWed 16. May 23:32:06 2012   
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateWed 16. May 23:24:48 2012

Date Generated: 05/16/2012 - 23:40:42