filterbank Project Status (05/17/2012 - 04:57:23) | |||
Project File: | FilterBank.xise | Parser Errors: | No Errors |
Module Name: | filterbank | Implementation State: | Synthesized (Failed) |
Target Device: | xa6slx16-3csg225 |
|
|
Product Version: | ISE 13.4 |
|
|
Design Goal: | Balanced |
|
|
Design Strategy: | Xilinx Default (unlocked) |
|
|
Environment: | System Settings |
|
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | ||||||
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
CPLD Fitter Report (Text) | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Out of Date | Thu 17. May 03:54:52 2012 |