System Settings

 
Environment Settings
Environment Variable xst ngdbuild map par
LMC_HOME c:\altera\11.0\quartus\eda\sim_lib\excalibur\swift < data not available > < data not available > < data not available >
PATHEXT .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.PSC1		 < data not available > < data not available > < data not available >
Path C:\Xilinx\13.4\ISE_DS\ISE\\lib\nt;
C:\Xilinx\13.4\ISE_DS\ISE\\bin\nt;
C:\Xilinx\13.4\ISE_DS\PlanAhead\bin;
C:\Xilinx\13.4\ISE_DS\ISE\bin\nt;
C:\Xilinx\13.4\ISE_DS\ISE\lib\nt;
C:\Xilinx\13.4\ISE_DS\common\bin\nt;
C:\Xilinx\13.4\ISE_DS\common\lib\nt;
C:\Program Files\FEKO\6.0\bin;
C:\WINDOWS\system32;
C:\WINDOWS;
C:\WINDOWS\system32\WBEM;
C:\bin;
C:\altera\quartus42\bin;
C:\altera\quartus42\eda\sim_lib\excalibur\swift\lib\pcnt.lib;
C:\WINDOWS\system32\WindowsPowerShell\v1.0;
C:\Program Files\IVI Foundation\IVI\bin;
C:\Program Files\IVI Foundation\VISA\WinNT\Bin\;
C:\PROGRA~1\IVIFOU~1\VISA\WinNT\Bin;
C:\Program Files\IVI Foundation\VISA\WinNT\Bin;
C:\Program Files\Microchip\MPLAB C32 Suite\bin;
C:\Program Files\Microchip\MPLAB IDE\VDI;
C:\Program Files\HI-TECH Software\PICC\PRO\9.65\bin		 < data not available > < data not available > < data not available >
XILINX C:\Xilinx\13.4\ISE_DS\ISE\ < data not available > < data not available > < data not available >
XILINX_DSP C:\Xilinx\13.4\ISE_DS\ISE < data not available > < data not available > < data not available >
XILINX_PLANAHEAD C:\Xilinx\13.4\ISE_DS\PlanAhead < data not available > < data not available > < data not available >
 
Synthesis Property Settings
Switch Name Property Name Value Default Value
-ifn   filterbank.prj  
-ofn   filterbank  
-ofmt   NGC NGC
-p   xa6slx16-3-csg225  
-top   filterbank  
-opt_mode Optimization Goal Speed Speed
-opt_level Optimization Effort 1 1
-power Power Reduction NO No
-iuc Use synthesis Constraints File NO No
-keep_hierarchy Keep Hierarchy No No
-netlist_hierarchy Netlist Hierarchy As_Optimized As_Optimized
-rtlview Generate RTL Schematic Yes No
-glob_opt Global Optimization Goal AllClockNets AllClockNets
-read_cores Read Cores YES Yes
-write_timing_constraints Write Timing Constraints NO No
-cross_clock_analysis Cross Clock Analysis NO No
-bus_delimiter Bus Delimiter <> <>
-slice_utilization_ratio Slice Utilization Ratio 100 100
-bram_utilization_ratio BRAM Utilization Ratio 100 100
-dsp_utilization_ratio DSP Utilization Ratio 100 100
-reduce_control_sets   Auto Auto
-fsm_extract   YES Yes
-fsm_encoding   Auto Auto
-safe_implementation   No No
-fsm_style   LUT LUT
-ram_extract   Yes Yes
-ram_style   Auto Auto
-rom_extract   Yes Yes
-shreg_extract   YES Yes
-rom_style   Auto Auto
-auto_bram_packing   NO No
-resource_sharing   YES Yes
-async_to_sync   NO No
-use_dsp48   Auto Auto
-iobuf   YES Yes
-max_fanout   100000 100000
-bufg   16 16
-register_duplication   YES Yes
-register_balancing   No No
-optimize_primitives   NO No
-use_clock_enable   Auto Auto
-use_sync_set   Auto Auto
-use_sync_reset   Auto Auto
-iob   Auto Auto
-equivalent_register_removal   YES Yes
-slice_utilization_ratio_maxmargin   5 0
 
Operating System Information
Operating System Information xst ngdbuild map par
CPU Architecture/Speed Intel(R) Core(TM) i5 CPU 760 @ 2.80GHz/2791 MHz <  data not available  > <  data not available  > <  data not available  >
Host bluelabvbox <  data not available  > <  data not available  > <  data not available  >
OS Name Microsoft Windows XP Professional <  data not available  > <  data not available  > <  data not available  >
OS Release Service Pack 3 (build 2600) <  data not available  > <  data not available  > <  data not available  >