filterbank Project Status (05/17/2012 - 04:57:23)
Project File: FilterBank.xise Parser Errors: No Errors
Module Name: filterbank Implementation State: Synthesized (Failed)
Target Device: xa6slx16-3csg225
  • Errors:
 
Product Version:ISE 13.4
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateThu 17. May 03:54:52 2012

Date Generated: 05/17/2012 - 05:04:27