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Very High Speed Integrated Circuit Hardware Description Language (VHDL) is a hardware description language that is gaining increasing popularity among digital designers in South Africa, as it is both a synthesis and simulation language. Many designers make use of the language’s synthesis ability but hardly tap into the power of its simulation abilities. This dissertation primarily investigated the feasibility of VHDL simulation during the design process. Secondary goals were to document the design methodology as well as state-of-the-art of the tools required for FPGA design and simulation. As a case study, a digital preprocessor for a synthetic aperture radar (SAR) was designed and simulated. The design was targeted for an FPGA in an attempt to determine the level of complexity of algorithm that can be obtained in an FPGA. This was a hardware solution to the design requirement; a completely software solution implemented in a DSP was attempted by Yann Tréméac .
In July 1993, the US Department of Defence instigated a program known as Rapid Application Specific Signal-processor Prototyping (RASSP). The purpose of this program was to review the process used in creating embedded digital signal processors in an attempt to decrease the time taken to produce a prototype by a factor of four. The methods proposed by RASSP for achieving this goal included the reuse of existing modules, concurrent design and virtual prototyping.
The virtual prototyping that the RASSP initiative refers to includes a process of writing VHDL models to represent the system being designed. These models are first written at an abstract level where the mathematical equations which describe the processing are tested. Test data can be input to the model which will perform the required processing. The output can then be verified to ensure that the equations are correct. At this stage, the model contains no structural information as to how the processing is achieved, nor even the numerical method used to implement the equations.
The level of abstraction of these models decreases with every model that is written. Obviously the number and type of models that are written depends upon the design. An example of the models which could be written are a mathematical model and an algorithm model which models the numerical methods used in implementing the mathematical equations. A behavioural or functional model can then be written to break the system into a number of sub-components. The sub-components are modelled so that their interfaces are correct but the internals contain no information on the structure used to implement the algorithms. These models can then be further refined to include implementation details until a final design is produced. At each stage, the test data that is used in the more abstract model can still be used for verification. This system of testing requires that testbenches be written. These are simply pieces of VHDL code that can read and write data files as well as provide known stimuli to the unit under test.
To investigate the feasibility of VHDL modelling, a preprocessor for the South African Synthetic Aperture Radar (SAR) was designed and modelled. This preprocessor was required to low pass filter the data received by the radar and then sub-sample it safely to reduce the data rate of the data to be stored. Three methods were considered for implementing this data reduction: Using a presummer, using a FIR filter or a combination of the two. The last option was chosen since it produced the highest azimuth resolution after SAR processing and it required the least number of filter taps to produce. The method required a presummer which summed three PRIs. The FIR filter was a 32 tap filter and incorporated a “skip” factor of 4. This method did not violate any constraints set by the SAR processing regarding the sampling rate of the data, and it was feasible to implement.
Since the processing was divided into the presummer and prefilter, it was logical that the hardware be similarly divided. One of the first design issues to be overcome was how these two entities should interact. Both required the use of external RAM to facilitate temporary data storage. The first method was to have separate memories for each entity. The presummer would then output a presummed range line to the prefilter for processing. The greatest disadvantage of this method was that the prefilter would then have to store this data in its memory before processing could take place. This was inefficient as the prefilter would have to store the data again in its memory and this would prevent it from processing during that time. The second method was the one implemented. The implementation made use of dual ported RAM. The presummer was connected to one port and the prefilter to the other. The advantage of this method was that the prefilter did not have to perform any data storage which increased the amount of time it could spend processing data.
An algorithm model was written for the presummer and prefilter operations to verify the effects of the precision of the stored data, the filter tap weights and the mathematical validity of the process. Test data was produced and read into the model. The processed data was output and the results analysed. This data set was then used to verify the operations of the other more detailed models.
The second model that was written was an abstract functional model. This modelled the interfaces of the presummer and prefilter but contained no details of the internal implementation or timing. The abstract functional model was however able to process data and the test data which was used in the algorithm simulation was used to verify the operation of the model. A model of the RAM had to be written to allow the presummer and prefilter to store data. A functional model was written which contained no timing information but contained the full functionality of the device being modelled.
Finally the presummer and prefilter descriptions were written to allow synthesis. A VHDL synthesiser was used to specify the logic required to implement the devices. FPGA design software was then used to place-and-route the logic and finally a FPGA configuration file was produced. Back-annotated VHDL source code was also produced by the FPGA design software. This was a gate level VHDL model of the device and included timing information which reflected the internal delays of the FPGA. This model was used in the test bench for the functional model since it contained the same I/O ports. The same test data was again used and the results compared to the functional simulation for verification.
In conclusion, the modelling provided a method of verification that would normally only be achievable with a physical prototype. The largest problem encountered with the virtual prototyping was the simulation time of the gate level models. These would have taken up to 60 days on an Intel PII-300MHz processor with 196MB RAM to perform - longer than the time required to build and debug a physical prototype. The second problem was the availability of VHDL models. Without simulation models of all the components used, system level simulation was a pointless exercise. There are some web sites which contain a number of free models but the majority of available models are commercial and are therefore expensive. For companies starting out in the field of VHDL modelling, the cost of a VHDL simulator package can also be prohibitive. If the required models are available and software to simulate and synthesise them, the goals of RASSP can be achieved.
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This dissertation describes the design and implementation of a radar simulator called Sarsim2. The radar simulator was originally developed to produce synthetic range profiles (SRPs) of complex aircraft models. It was then expanded and upgraded to generate simulated synthetic aperture radar (SAR) data.
Over the last few years a substantial amount of work has been carried out by the Radar Remote Sensing Group (RRSG) at the University of CapeTown (UCT) to produce SRPs of aircraft using an L-Band search radar of Reutech Systems. The high range resolution that can be obtained from SRP processing makes it feasible to extract characteristic features from a profile obtained from an aircraft. The ultimate aim of producing SRPs is to use these extracted features for non-cooperative target recognition (NCTR), i.e. to be able to identify an aircraft type from the echo signal received by the radar. The radar simulator was written to produce SRPs of aircraft models, which could then be used to investigate the feasibility of various aircraft-identification algorithms.
The stepped-frequency processing required to obtain SRPs of aircraft targets has initiated further research in the RRSG into more efficient stepped-frequency processing techniques, and the radar simulator has been used extensively to generate simulated data.
The RRSG group is also actively involved with SAR processing techniques, and the radar simulator has been invaluable in providing necessary simulation data to test various processing algorithms.
One of the main objectives of this simulator was to have an easy-to-use graphical interface, which can show results in real-time. This requirement makes it necessary to find some way of reducing the required computation. The solution implemented may be called WYSIWIC (what you see is what is calculated). This means that the data is only calculated to a resolution depending on the screen resolution. Only when the data is saved to disk will it be calculated and written with the required sampling rate.
Some of the features of the radar simulator include:
The program has been kept flexible so that features (for example using real-life antenna gain patterns) can be loaded with ease.
The graphical frontend of the simulator was initially written in C++ using the Object Windows Library (OWL) from Borland C++ 5.0, but was then rewritten with Borland C++ Builder, which made the development much easier. Borland C++ Builder (BCB) can be cnosidered as the best Rapid Application Development (RAD) tool currently available, offering visual components combined with the flexibility and speed of C++. The simulator exploits the protected memory model of 32 bit programs which has the advantages of crash protection and practically no memory restrictions. It therefore has to run under either Windows 95 or Windows NT 4.0. For portability reasons all the code (except the windows front end) has been written in ANSI C++. All processor intensive calculation routiens have been written as threads. This makes other tasks running in the background more responsive and also enables the user to abort a calculation at any time.
A second program has been included, which is basically the same program without the graphical frontend. This program is portable as it is written in pure ANSI C++. It performs like a compiler which reads the script files (text files) and writes the required simulation files to disk.
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The purpose of this dissertation is to investigate the feasibility of using neural networks in conjunction with the Fourier Modified Direct Mellin Transform (FMDMT) for the recognition of ship targets. The FMDMT is a modification of the Direct Mellin Transform for digital applications, and is applied to the magnitudes of the Discrete Fourier Transforms (DFT) of range profiles of ships. Necessity for the use of the FMDMT is corroborated by the fact that faetures can be extracted from the range profiles of targets, regardless of target aspect angle. Variation in aspect angle results in variation of the independent variable. Feature extraction is made possible by the scale invariant properties of the Mellin Transform.
Substantial emphasis was placed on preprocessing techniques applied in the implementation of the FMDMT on simulated range profiles and in particular, real ship profiles. The FMDMT was thus examined extensively and utilised as it was developed and demonstrated in ... At the completion of this examination, the recognition procedures and methods were applied on simulated data with the aid of a radar simulator developed and adapted for this dissertation. Results of the recognition of simulated ship targets were scrutinised closely and recorded. Employment of this procedure afforded the ability to compare the recognition results for real ship data with those of simulated ship data at a later stage.
Acquisition of a large database of ship profiles was made successful by a ship target data capture plan implemented at the Institute for Maritime Technology (IMT) in Simon's Town. The database included the radar range profile data for the SAS Protea and Outeniqua, which carried out several successful full circular manoeuvres in the line of sight of the search radar utilised (Raytheon). The relevant ships performed these circular manoeuvres in order that the acquired data incorporate radar range profiles of the relevant ships at most aspect angles from 0 degrees to 360 degrees. Extensive and thorough testing of the performance of the FMDMT would thus be possible since every possible aspect angle would be scrutinised. Preprocessing of data and recognition of targets was implemented in exactly the same manner and order as was the case with the simulated ship data.
Extensive examination of the FMDMT revealed that the MDMT should only be applied to one side of a real and even Fourier Transform of a ship target. Literature on the FMDMT had failed to operate on this point.
Comparison of the recognition results for real and simulated data, indicates a great similarity in success, thus validating the methods and procedures described theoretically and adopted practically for preprocessing of the radar range profiles and recognition of the targets.
In order to demonstrate the feasibility of ship target recognition using the procedures and methods incorporated in the dissertation, real ship data for an entire range of different ships could be acquired in the same manner as indicated above.
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